The availability of intelligent embedded system to assist the classification application is a great challenge in machine learning field in last few decades. Extreme Learning Machine (ELM) is one of the best learning methods for the implementation due to its classification accuracy and speed. The main computational effort of ELM is to compute the pseudo-inverse of hidden layers output. This work presents a Modified Gram-Schmidt QR decomposition (MGS-QRD) method and hardware architecture for the FPGA implementation of ELM system. The proposed algorithm is implemented on MATLAB and compared with ordinary ELM computational methods. Next, an embedded ELM system is presented, where the software part is developed using C language and hardware is created on field-programmable gate array (FPGA). Experimental results show that the proposed algorithm achieve better performance than original ELM computational method. Finally, the investigation is performed by altering the activation function and number of hidden neurons, providing a guideline on selecting the best parameter for classification.

Some of Internet services require users to provide their sensitive information such as their name, address, credit card number, and an ID-password pair. In these services, the manner in which the provided information is used is solely determined by the service providers. As a result, even when the manner in which information is used by a service provider appears vulnerable, users have no choice but to allow such usage. Therefore, we have proposed a user customized data protection framework that enables users to select the manner in which their sensitive information is protected. In our framework, a user selects a policy that defines the manner in which his/her information is to be protected and its manner defined by the policy is incorporated into a program. By allowing a service provider to the information provided by a user through the program, the user can protect his/her sensitive information in a manner selected by him/her. This framework works well when existing a manner (protection policy) which is tolerant to the alteration of the program, otherwise, a program alteration might be a concern. Therefore, in this paper, we attempts to protect a customized program by using program obfuscation and sanitizable signature techniques. © 2011 IEEE.

Some of Internet services require users to provide their sensitive information such as credit card number, and an ID-password pair. In these services, the manner in which the provided information is used is solely determined by the service providers. As a result, even when the manner in which information is used by a service provider appears vulnerable, users have no choice but to allow such usage. In this paper. we propose a framework that enables users to select the manner in which their sensitive information is protected. In our framework, a policy, which defines the type of information protection, is offered as a Security as a Service. According to the policy, users can incorporate the type of information protection into a program. By allowing a service provider to use their sensitive information through this program, users can protect their sensitive information according to the manner chosen by them.

We propose the Fuce (FUsion of Comunication and Execution) architecture. The Fuce processor of the architecture executes all processing composed of fine-grain "uninterruptible" threads. The multiple thread execution model of the architecture takes the continuation-based multithreading model. The execution model takes dependency among threads as the continuation instruction. The parallel I/O processing with the execution model divides I/O processing into fine-grain threads, and associates in Chip Multiprocessor as processor cores and fine-grain threads. In this paper, the parallel I/O processing in the continuation-based multithreading compares the parallel I/O processing with interrupt. This paper shows the parallel I/O processing performance is almost equal, and the response time in the continuation-based multithreading can be shortened.

We propose the Fuco architecture based on dataflow computing model. The goal of this architecture is fusion of communication and execution. The multiple thread execution model of the architecture takes the continuation-based multithreading model that manages dependency among fine-grain "uninterruptible" threads. In this paper, the continuation-based multithreading model constructs more resourceful parallel I/O processing cooperated with by processor and operating system. Our model is different from the conventional I/O processing model that handles "interrupt." We illustrate the continuation-based parallel I/O processing model.

Current trends of research on multithreading processors are the chip multithreading (CMT), which aims to exploit thread level parallelism (TLP) and to improve performance of software built onalltraditional threading components, e.g. pthreads. However, CMT is principally a straight forward extension of conventionalall symmetric multiprocessor (SMP) techniques, and it will suffer from the same limits to scalable multithreaded processing ifallit is built only on the traditional sequential-computation-based framework. Consideringallthese limitations of sequential-processor-basedallmultithreading, we are taking another approach to developing a multithreading processor dedicated to thread level parallelism(TLP). Our processor, named Fuce, is based on continuation-based multithreading. A thread is defined as a block of sequentially ordered instructions which areall executed exclusively. Every execution of a thread is triggered by one or more events, each of which is called continuation. The hardware cost and performance of the Fuce processor areallevaluated by means of a hardware implementation on FPGA and software simulation. Copyright 2007 ACM.

We are developing the FUCE processor based on the dataflow computing model. FUCE means FUsion of Communication and Execution. In order to execute many threads with multiple thread execution units efficiently, the FUCE processor executes multiple threads using the exclusive multi-thread execution model. The core concept of the exclusive multi-thread execution model is continuation based multi-thread execution, which is derived from dataflow computing. The FUCE processor unifies processing inside the processor and communication with processors outside as events, and executes the event as a thread. In this paper, we introduce the thread-programming model and the architecture of the FUCE processor and evaluate the hardware cost of a FUCE processor and the concurrency performance of a FUCE processor which we described in VHDL. As a result, we understood that the processor has concurrency capability when there is sufficient thread level parallelism.

This paper proposes an on-chip-memory processor architecture: FUCE. FUCE means Fusion of Communication and Execution. The goal of the FUCE processor project is fusing the intra processor execution and inter processor communication. In order to achieve this goal, the FUCE processor integrates the processor units, memory units and communication units into a chip. FUCE Processor provides a next generation memory system architecture. In this architecture, no data cache memory is required, since memory access latency can be hidden due to the simultaneous multithreading mechanism and the on-chip-memory system with broad-bandwidth low latency internal bus of FUCE Processor. This approach can reduce the performance gap between instruction execution, and memory and network accesses.

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