The charging efficiency of a lithium-ion capacitor (LIC) is an important problem. Until now, due to the stepwise charging method, the charging efficiency of 95.5% has been realized. However, the problem is that the issue of what level the charging efficiency can be increased to, is yet to be well investigated. In this article, the problem is investigated under the galvanostatic charging condition. The charging efficiency is measured as a function of the charging current. As a result, it can be more than 99.5% when the charging is quasi-static, in other words, an adiabatic process is realized. Next, the problem of how much energy can be taken out from the energy-stored capacitor is investigated with a load resistor circuit. It is clarified that the discharging energy from the capacitor is equal to the stored energy in the case when a load resistor is used and the discharging is quasi-static. It is confirmed that LICs are suitable for use as energy storage devices.

キャパシタを定電流充電で一定時間充電したときに，蓄積される電気エネルギーとキャパシタ容量の関係を導き，最も電気エネルギーが大きくなるときの容量値を導出した．またこのときの充電効率と容量との関係についても明らかにする．

An adiabatic reversible circuit was designed for charging a Lithium ion capacitor. The duty ratio of the switching transistors is digitally controlled by a microprocessor. A Lithium ion capacitor has the minimum and the maximum operating voltage. Therefore, the charging voltage is set to be in that range. Using this energy storage system, it is clarified from the experiment that the efficiency is 95.5% during charging and also discharging process. Then the total efficiency is 91.2% during one cycle, which is the best value in the proposed stepwise adiabatic charging circuit.

An adiabatic circuit was designed for dissipationless charging of a capacitor. The duty ratio of the switching transistors is changed stepwise and controlled by a microprocessor. The charging efficiency, that is the ratio between the work done by the power supply and electrostatic energy of the capacitor, is calculated from experimental results. The efficiency is 94% when the number of stepwise voltage is 32, which is consistent with the theoretical value.

An adiabatic circuit was designed for charging and discharging a supercapacitor stepwise. The duty ratio of the switching transistors is changed in a stepwise fashion and controlled by a microprocessor. The charging efficiency, that is the ratio between the work done by the power supply and electrostatic energy of the capacitor, is calculated from experimental results. The efficiency is 95% when the number of stepwise voltage is 32, which is consistent with the theoretical value.

A circuit for adiabatically charging and discharging a supercapacitor was designed. A microprocessor sets the duty ratio of the switching transistors that control the inductor current. Changing the duty ratio in a stepwise fashion causes the output voltage to change in a similar fashion. Stepwise voltage changes enable adiabatic charging and discharging. Current measurements showed that the eight-step charging and discharging of a supercapacitor reduced the energy dissipation to one-eighth of that for a constant-voltage process. The circuit enables precise voltage control in small steps.

Energy storage technology is becoming more and more important in today's environmentally conscious society. In the conventional method of directly charging a capacitor under a constant power supply voltage, the amount of energy dissipation is the same as the energy stored in the capacitor. In this paper, we propose the stepwise charging of a capacitor by consecutively changing the duty ratio of the DC-DC down converter. In step charging, the energy dissipation is reduced to one Nth when compared with the conventional direct charging. The reduction of the dissipated energy is verified by SPICE simulations and by breadboard experiments, through which an energy reduction of one fourth and one eighth is confirmed from the measured power supply currents in four and eight step charging, respectively.

A single-bit-line (BL) static RAM (SRAM) circuit that employs adiabatic charging of a word line during a read operation was found to provide a large dynamic noise margin (DNM) for reading. Single-BL reading is achieved by using a left access transistor and a shared reading port. The shared reading port greatly reduces the BL capacitance, enabling the voltage of the BL connected to the low-voltage node of the flip-flop to change from the precharge voltage to GND. An analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit. This circuit enables the design of an SRAM that is smaller than a conventional one, resulting in lower energy consumption.

This paper describes characteristics of stepwise adiabatic charging with an inductor current by controlling switching transistors. An exact analytical resolution is obtained by using a vector comprising a voltage and a current. From a matrix calculation, the voltage and current can be written with solutions of the characteristic equation, power supply voltage, the switching ratio in the switching transistor circuit, and the number of switchings. Using the expression, the voltage and current in the stepwise adiabatic charging method can be derived clearly. As a result, it is clarified analytically that, in N-step charging, the current is reduced to 1/N so that the energy dissipation is reduced to 1/N. Next, the experimental switching transistor circuit with the controller is described, which is composed of discrete ICs. The experimental inductor current in the circuit is investigated. The measured current is reduced to 1/N in N-step charging, which is consistent with the simulated one from the theory. It is also confirmed experimentally from the average power supply current that power consumption is reduced to 1/N.

A stepwise-voltage-generation circuit was devised that is based on a capacitor bank and that dissipates no energy when a stepwise voltage is generated. The stepwise voltage is generated spontaneously, and depends neither on the initial voltages to the capacitors nor on the switching order. A new adiabatic-charging circuit based on this circuit was also devised that increases the voltage in a stepwise fashion. The total capacitance of the capacitors in the regenerator is much smaller than a load capacitance, which enables construction of a very small adiabatic regenerator. This regenerator cannot be made with a conventional circuit, which uses a tank capacitor that is much larger than a load capacitor for adiabatic charging.

Thin film Al2O3/Al-rich Al2O3/SiO2 structures were fabricated on p-Si substrates. Radio-frequency magnetron co-sputtering was used to form Al-rich Al2O3 thin film as the charge-trapping layer of nonvolatile Al2O3 memory. Capacitance-voltage measurements showed a large hysteresis due to charge trapping in the Al-rich Al2O3 layer. The charge trap density was estimated to be 42.7 x 10(18) cm(-3), which is the largest value ever reported for an Al-rich Al2O3 layer; it is six times larger than that of a conventional metal-nitride-oxide-silicon memory. Thermal annealing was found to reduce the leakage current of the Al2O3 blocking layer, thereby providing this structure with better data retention at room temperature than an as-deposited one. In addition, the annealed structure was found to exhibit good data retention even at 100 degrees C. (C) 2013 Elsevier B.V. All rights reserved.

The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the stepwaveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory.

This study describes a method to easily predict the write yield of a static random access memory (SRAM) memory cell. The differential coefficient of the combined word line margin (CWLM) for the threshold voltage (V-th) is analysed using the simple Schockley's transistor model. The analysis shows the good linearity comes from keeping the access transistor operating in the saturation mode for a wide range of V-th's. The Monte Carlo simulation demonstrates that the CWLM obeys the normal distribution. The mean and the variance of the CWLM are almost constant for sample numbers ranging from 100 to 100 000. The estimated write failure probability are almost uniform within a factor of 1.7 for the number of samples more than 300, which allows us to evaluate SRAM with a small number of measurements. The predicted distribution using the differential coefficient calculated by the SPICE simulation also matches the Monte Carlo results. The estimated write failure probability agrees with the Monte Carlo results within a factor of 2.0, which is acceptable for SRAM redundancy circuit design. Finally, the write yield is related to the error rate. Thus, the write yield is easily predicted from a small number of measured samples or the differential coefficients of the CWLM on the V-th's calculated by the SPICE simulation.

Adiabatic charging and discharging of a capacitor with an inductor current by controlling switching transistors is demonstrated experimentally. First, we designed an eight-step charging and discharging circuit. The switching transistor ratio is designed to range from zero to one in one-eighth steps. By changing the switching transistor ratio stepwise, output voltage is generated stepwise. Using the stepwise voltage, adiabatic charging and discharging can be performed. In N-step charging, it is clarified that the energy dissipation is reduced to 1/N from the measurement of the power supply current, compared with the conventional charging and discharging of a capacitor.

A thin-film structure comprising Al2O3/Al-rich Al2O3/SiO2 was fabricated on Si substrate. We used radio-frequency magnetron co-sputtering with Al metal plates set on an Al2O3 target to fabricate the Al-rich Al2O3 thin film, which is used as a charge storage layer for nonvolatile Al2O3 memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. For a fabricated Al-O capacitor structure, we clarified experimentally that the maximum capacitance in the C-V hysteresis agrees well with the series capacitance of insulators and that the minimum capacitance agrees well with the series capacitance of the semiconductor depletion layer and stacked insulator. When the Al content in the Al-rich Al2O3 is increased, a large charge trap density is obtained. When the Al content in the Al-O is changed from 40 to 58%, the charge trap density increases from 0 to 18x10(18) cm(-3), which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for low-cost nonvolatile memory. (C)11 Elsevier B.V. All rights reserved.

Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vth's) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vth's are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski et al. was found to be the most suitable definition for predicting the distribution and the write yield.

An accelerated evaluation method for the SRAM cell write margin is proposed based on the conventional Write Noise Margin (WNM) definition. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is used because the access transistor operates in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The amount of WNM shift is determined from the WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. A normal distribution of the AWNM drastically improves development efficiency, because the write failure probability can be estimated by a small number of samples. Effectiveness of the proposed method is verified using the Monte Carlo simulation. © 2011 IEEE.

Adiabatic charging of a capacitor with a step down converter by changing the duty ratio is considered. First, for a profound understanding of the circuit, the general analytical solution of step down converter is considered. It is confirmed that the system can be resolved analytically and that the equilibrium state of current and voltage are consistent with SPICE simulation. Next, adiabatic charging by changing the duty ratio is investigated. From SPICE simulation, it is confirmed that energy dissipation is reduced to one-fourth when four-step charging is used. By increasing the step number, energy dissipation decreases to zero and dissipationless operation is achieved.

A 64-kb SRAM circuit with a single bit line (BL) for reading and with two BLs for writing was designed. Single-BL reading is achieved by using a left access transistor and a left shared reading port. We designed the cell layout and confirmed that there is no area penalty for producing two word lines in a memory cell. An analysis of butterfly plots clearly confirms that the single-BL SRAM has the larger static noise margin than the two-BL one. It is confirmed that the static noise margin in the single-BL SRAM is further increased when the BL is precharged to not VDD but to the lower value in the range of VDD/2 to 3VDD/4. In addition, a new sense amplifier circuit without reference voltage is proposed for single-BL reading. We also propose a divided word line architecture for writing to maintain the static noise margin for unwritten blocks.

This study considers a method for minimising the energy dissipation when charging a variable-gap capacitor. The authors assume a capacitor coupled with repulsive mechanical potential energy. The potential energy is proportional to 1/d(n), where d is the plate distance. With this capacitor model, the authors use the method of Lagrange multipliers to investigate a way to minimise the energy dissipation. When n = 3 (Q = pV(2) is satisfied in this case), the authors confirm that the conventional equal-step charging does not minimise the energy dissipation. From the viewpoint of the charge transfer per step, conventional constant-charge-transfer charging does not minimise the energy dissipation, but increasing-charge-transfer charging (small charge transfer at the initial step and large charge transfer at the final step) does minimise the energy dissipation. From analyses of the charging and discharging processes, it becomes clear that the ratio of energy dissipations between the conventional and proposed methods approaches 0.89 when the step number increases. This means the proposed method reduces the energy dissipation by 11% compared with the conventional one. A circuit that enables the minimum energy dissipation as discussed above is also described.

We discuss the stability of an adiabatic stepwise-charging circuit with advanced series capacitors, which is effective for the reduction of the applied voltage to each capacitor. SPICE simulation shows that this circuit is stable even if the initial voltages are lower than zero. For the analytical discussion, we derive a matrix that connects charge and voltage in the circuit and show that the matrix is a positive-definite symmetric one. Therefore, the step voltage is generated spontaneously. We also derive energy dissipation analytically using tank capacitor voltage. Using this formula and SPICE simulation, we clarify that energy dissipation decreases monotonically as a function of time and finally reaches the minimum value.

The SRAM operating margin in 65nm technology is analyzed. The peak characteristic in the read margin versus the supply voltage was found to be caused by the channel length modulation effect. Controlling the memory cell virtual ground line proved to be effective in enlarging the operating margin simultaneously in the read and the write operations. A simple o ptimum circuit which does not require any dynamic voltage c ontrol is proposed, realizing an improvement in the operating m argin comparable to conventional circuits requiring dynamic voltage control. © 2010 IEEE.

An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of V-T variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.

An adiabatic 1-kb SRAM circuit was designed, which enables gradual charging during writing and reading while maintaining a large VDD so that the problems of V-T variation and electromigration in the nanocircuit can be resolved. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that the memory cell power line is set in a high-impedance state. Then, we can write data easily by inputting adiabatic signal from one bit line, while the other bit line is set to ground. For reading, a verifying operation is proposed for resolving the electromigration problem. The word line voltage is changed stepwise while the voltages of the bit lines are verified. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and found that there is no area penalty. In addition, a new charge recycle circuit with tank capacitors is proposed.

Adiabatic operation promises large reductions of power consumption because it does not dissipate energy. This paper reviews recent progress in adiabatic circuits. First, a charge recycle regenerator with the tank capacitor is discussed. Next, an adiabatic charging binary decision diagram circuit is discussed. In the circuit, a gate-level pipeline can be realized by using four charge-recycling clocks. Also reviewed is an adiabatic circuit based on clocked energy reversible logic, which can maintain the complementary-metal-oxide-semiconductor circuit architecture. Finally, adiabatic staticrandom-access-memory is covered, which is structurally close to the conventional SRAM. These adiabatic circuits are very effective in the nanoscale region because they can avoid hot carrier effects and electromigration owing to their gradual charging characteristics. This review also covers some important recent patents. © 2009 Bentham Science Publishers Ltd.

Radio-frequency magnetron cosputtering by setting an Al metal plate on an Al2O3 target is an effective method for fabricating Al-rich Al2O3 thin film, which is used as a charge storage layer for nonvolatile Al2O3 memory. The wet etching rate of the fabricated AlO film increases with Al content. The optical transmittance decreases when the Al content in AlO increases. Using rf magnetron cosputtering, the authors fabricated an Al2O3 film with an embedded Al-rich Al2O3 and investigated the charge trapping characteristics after a 30 min annealing at 550 degrees C. C-V characteristics indicate that the Al-rich Al2O3 structure is very stable after annealing. The charge trap density in Al-rich Al2O3 after annealing is much larger than that in stoichiometric Al2O3. (c) 2008 American Vacuum Society.

An adiabatic quasi 6T-SRAM is proposed in which a memory cell shares the writing and reading ports between a flip-flop and a bit line so that the transistor number in a memory cell is decreased to about six. The gradual charging operation in the circuit can avoid electromigration and hot carrier effects. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually by using a high-resistivity nMOSFET, and the nMOSFET is turned of to set the memory cell power line in a high-impedance state. Then, adiabatic signal from the shared writing port is input to charge the memory cell power line to VDD. In the reading mode, the shared reading port, which connects the flip-flop and the bit line, is used for stable operation. The bit line can be precharged to a small value ( for example, VDD/4), which enables a small current flow during the reading mode. Logic data are read by sensing the voltage decrease in the precharged bit line.

The stability of a new adiabatic circuit with inductive load is discussed. The adiabatic circuit generates quasi-sinusoidal waveform current with multiple power- supply voltages. SPICE simulation shows that this circuit is stable after damping oscillation. For the analytical discussion, we derive a matrix that connects charge, current, and voltage in the circuit. By using matrix theory and a physical consideration, it is proved that the absolute value of the eigen value of the matrix, which connects the initial voltage and current deviations from the equally- divided- stepwise mode with those after the charge- recycling process, is smaller than 1. Therefore, the voltage and current deviations become zero after many charge- recycling processes. The circuit might be useful for a DC- AC inverter in the power electronics.

The stability of a new adiabatic stepwise charging circuit with an asymmetric 1D capacitor array is discussed. SPICE simulation shows that this circuit, like the one with a symmetric array, is stable. For the analytical discussion, we derive a matrix that connects charge and voltage in the circuit with the asymmetric 1D-capacitor array and show that the matrix is the positive-definite symmetric one. Using matrix theory, it is proved that the eigen value of the matrix connecting the initial voltage deviation from the step value with that after the charge-recycling process is smaller than 1. Therefore, the voltage deviation becomes zero after many charge-recycling processes.

This paper considers the energy consumed by charging and discharging a width-variable capacitor. The capacitor with plate distance d is coupled with repulsive mechanical potential energy, which is proportional to 1/d(n). In this capacitor model, there is a stable point between attractive electrical force and repulsive mechanical force. All energies, including the electrostatic energy, potential energy, and energy dissipation, are proportional not to the ordinary value V-2 but to V2/(n-1)+2, where V is the abrupt power supply voltage. We apply N-stepwise adiabatic charging to the width-variable capacitor system. It is shown that the energy consumption after charging and discharging (or recycling) can be 1/N times smaller than that of the conventional abrupt operation. By increasing the step number N, the adiabatic operation can ideally charge and discharge the width-variable capacitor system with absolutely no energy dissipation, although the voltage dependence of energies is quite different from the usual one. Adiabatic charging is very promising for realizing dissipationless operation in the proposed system. (c) 2007 American Institute of Physics.

This paper considers a more generalized capacitor that can decrease its width using its own electrical force. We consider a model in which the capacitor with plate distance d is coupled with repulsive mechatronical potential energy, which is proportional to 1/d(n). In the conventional case, n is considered to be approximately very large. In our capacitor model, there is a stable point between attractive electrical force and repulsive mechatronical force. In this system, electrostatic energy is equal to the sum of mechatronical potential energy and energy dissipation. Moreover, the mechatronical potential energy is 1/n times smaller than the electrostatic energy. All energies, including the electrostatic energy, potential energy, and energy dissipation, are proportional not to ordinary value V-2, but to V2/(n-1)+2, where V is the power supply voltage. This means the voltage dependence of energy is unusual. It is strongly dependent on the capacitor matter, i.e., on the characteristics of the mechatronical system. In addition, the energy dissipation of the system can be reduced to zero using the adiabatic charging process.

The stability of a new adiabatic stepwise charging circuit is discussed. Tank capacitors are connected in series between the power supply and ground. This circuit features immediate operation using a stepwise waveform, even if the tank-capacitor value is considerably larger than the load capacitance. This immediate operation is possible because stepwise voltage is formed immediately due to the voltage division by series capacitances. For the analytical discussion, we derive a voltage equation that connects the initial state and the final state after the charge-recycling process. It is proved that the eigen value of the matrix is smaller than 1. Therefore, a step waveform is spontaneously generated after many charge-recycling processes.

The simplified adiabatic SRAM is proposed which enables gradual charging during writing mode so that problems of electromigration and hot carrier effects can be resolved. For simplicity, we do not use a regenerator circuit for charge recycling in the circuit. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that we set the memory cell power line to be in a high-impedance state. Then, we input adiabatic signal from one bit line to charge the memory cell power line to V-DD. This writing method enables gradual discharging and charging. As for reading, the word line voltage is decreased to V-th, or it is changed stepwise while the voltages of bit lines are verified. These reading methods enable the gradual change. With the gradual charge transfer in writing and reading modes, the SRAM can avoid electromigration and hot-carrier effects even in the less-than-45-nm process, while it maintains an operating voltage of 1 V or more.

This article describes the fabrication process and capacitance-voltage (C-V) characteristics of a new non-volatile Al2O3 memory with nanoscale thin film deposited by electron-cyclotron-resonance sputtering. Al-rich Al2O3 shows characteristics somewhere between Al and Al2O3 in the refractive index and wet etching rate. C-V characteristics of Al-rich Al2O3 memory show a large hysteresis window due to the Al-rich structure, while there is no hysteresis window in the case of stoichiometric Al2O3. This memory is expected to stay non-volatile for several years or more because the capacitance value after writing and erasing operation remained at most unchanged after 4 h at T = 85 degrees C. Also, another new memory structure comprising SiO2/Al2O3 and the Al-rich Al2O3 structure is proposed, which features increased mobility due to the reduction of electron scattering at the Si/Al2O3 interface.

The stability of adiabatic stepwise charging reversible logic is discussed from the viewpoint of coupled oscillators. For adiabatic logic with asymmetric tank capacitors, we derive a matrix that connects the initial voltage with the voltage change after the charge-recycle process. This matrix is the same as the mechanical oscillator matrix of a string with equally spaced beads having different mass. From the theory of normal modes in coupled oscillators, it is proved that the eigenvalue of the matrix connecting the initial voltage with the final one is less than 1, which shows that a step waveform is spontaneously generated after many charge-recycle processes.

This letter describes the capacitance-voltage (C-V) characteristics of a new nonvolatile Al2O3 memory with nanoscale thin film deposited by electron-cyclotron-resonance sputtering. Al-rich Al2O3 was fabricated at a reduced oxygen gas flow rate and used as a charge storage layer of the Al2O3 memory, which is located between the tunnel insulator and blocking insulator. C-V characteristics show a large hysteresis window due to the Al-rich structure, but there is no hysteresis window in the case of stoichiometric Al2O3 structure. This memory will stay nonvolatile for several years or more. The number of electrons injected into the insulator in the case of nanoscale memory cell length is discussed. A discussion of the statistical Gaussian distribution indicates that about 50 localization sites are necessary in Al2O3 memory with 10 nm cell length for realizing a 1.8 V change of the threshold voltage, which corresponds to the control of ten electrons in the insulator. This structure is easily achieved by the proposed Al-rich Al2O3 memory. (c) 2005 American Institute of Physics.

The stability of adiabatic stepwise charging reversible logic is discussed. In the case of adiabatic logic with asymmetric tank capacitors, we derive a matrix which connects the initial state and the final state after the charge-recycle process. From the analytical discussion, it is proved that the absolute value of the eigen value of the matrix is less than 1. Therefore, it is shown that a step waveform is spontaneously generated after many charge-recycle processes. Next, an adiabatic stepwise charging SRAM is proposed. The SRAM is immune to hot-carrier effects and electromigration even in the less-than-45-nm process, while it maintains an operating voltage of 1V or more. The SRAM is suitable for nanoscale circuits.

The memory characteristics of a new non-volatile Al2O3 memory deposited by electron-cyclotron-resonance sputtering are described. Al-rich Al2O3 was fabricated at a reduced oxygen gas flow rate. Capacitance-voltage characteristics show a large hysteresis window owing to the Al-rich structure. This memory will stay non-volatile for several years or more.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and I MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

An adiabatic charging binary decision diagram circuit (AC-BDD) is proposed that uses pass transistor logic based on a BDD and is operated by four power clocks. The AC-BDD circuit has the characteristics of a gate-level pipeline. Also proposed is a simplified switched capacitor regenerator that operates stably at any time even if the load capacitance changes variously. An 8 x 8 bit multiplier was designed using 0.25-mu m CMOS/SIMOX (Complementary MOS/Separation by IMplanted OXygen) technology to confirm charging recovery. We found that the multiplier operates at 0.2 V and 1 MHz and its power consumption can be decreased to less than 10% that of CMOS logic.

We investigate how the mobility and carrier density of AlGaAs/GaAs two-dimensional electron gas are influenced by the fabrication process with plasma-excited chemical vapor deposition (plasma-CVD) SiN film. These properties are greatly reduced by annealing with plasma-CVD SiN film as a cap but are restored by reannealing after removing the SiN film. We further use capacitance-voltage measurements to investigate the influence of this same process on a more simplified structure, Si-doped GaAs layer. Annealing with a plasma-CVD SiN film changes the defect density of Si-doped GaAs in two, temperature dependent ways: annealing below 380 degrees C reduces deposition damage, and annealing above 300 degrees C produces new defects, which might be caused by the film stress. These new defects can be reduced by reannealing after removing the SiN film. (C) 1995 American Institute of Physics.

Spin-orbit interaction in InGaAs/InAlAs quantum wires is investigated by measuring conductance fluctuations at temperatures ranging from 2 K down to 0.06 K. The resistance of an InGaAs/InAlAs wire in a zero magnetic field decreases as the temperature decreases below 1.6 K. This temperature dependence is reproduced by the theory of antilocalization in the strong spin-orbit interaction regime. In the same temperature range, the conductance fluctuation amplitude increases nonmonotonically with decreasing temperature. This behavior is attributed to the temperature-induced transition from the weak to the strong spin-orbit scattering regime in the mesoscopic disordered system.

We investigated how the mobility, mu, and carrier density, n(s), of AlGaAs/GaAs two-dimensional electron gas (2DEG) are influenced by fabrication processes using plasma-excited chemical vapor deposition (plasma-CVD) SiN film. Annealing with plasma-CVD SiN film as a cap results in a large reduction in mu, and n(s). Both, however, are restored by reannealing after removing the SiN film. We further investigated the influence of the same process on a more simplified Si-doped GaAs layer structure through capacitance-voltage (C-V) measurements. Similar degradation and restoration of the carrier density were also observed for Si-doped GaAs. The reannealing temperature dependence shows the degraded carrier density is almost perfectly restored by reannealing at the low temperature of 380 degrees C for 20 minutes. Reannealing after removing the plasma-CVD SiN film is necessary for fabricating high-quality buried structures.

Buried wires with lateral potential barriers provided by AlGaAs/GaAs heterointerfaces have been fabricated by wet etching and metalorganic chemical vapor deposition regrowth. Burying the wire was proven to enhance the electrical transport properties; for example, it decreased the critical width and increased the subband energy separation. Two-dimensional simulation using the Poisson equation was performed to obtain the potential profile of both as-etched and buried wires. The quantum energy levels corresponding to the lateral confinement were calculated for the obtained potential profiles. The calculated energy separations agreed well with the experimental ones and the subband energy separation of the buried wire was larger than that of the as-etched wire for the same effective width. These results show that burying wire is effective for creating strong lateral confinement.

Boundary scattering in quantum wires is investigated as a function of the transverse mode number, N, using a split-gate configuration. The sepcularity factor, p, of boundary scattering is found to increase toward 1 with decreasing N. Taking into consideration that the boundary roughness in the split-gate quantum wires, which is caused by the random positions of the ionized-impurity ions in the doped layer, increases as the split-gate voltage decreases, then the increase in the specularity indicates decreased intersubband scattering due to the reduction of the mode number.

Buried wires with lateral interfaces consisting of AlGaAs/GaAs heterointerfaces are fabricated using wet etching and regrowth by MOCVD. The critical width of the buried wires was decreased to 0.1 mum, which was less than third of that of as-etched wires. The energy separation of one-dimensional subbands obtained from the Landau plots of Shubnikov-de Haas oscillations for the buried wires was increased to 2.8 meV, which was about two and half times larger than that of the as-etched wire. These results show that the buried quantum wire structure improves electrical transport properties.

A quantum dot is formed in AlxGa1-xAs/GaAs using the split-gate method. First the characteristics of the point contact, which determine the electron transport in the quantum dot, are investigated. Quantized conductance peculiar to the one-dimensional subband is observed. Next the transport properties of the quantum dot are studied by changing the voltage of the back gate, which is placed about 360 mum from the dot. Coulomb-blockade oscillations are observed before the current is completely pinched off. The charging energy of the dot is estimated to be about 0.6 meV based on the temperature dependence and source-drain voltage dependence of the oscillations. It is clarified experimentally that only the mutual capacitance between the back gate and the dot determines the oscillation period.

Small tunnel barrier were formed on AlxGa1-xAs/GaAs by focused-ion-beam implantation. The samples were then measured with dc current at 4.2 K, and the I-V curves revealed two distinct regions depending on applied bias: a tunneling region at small bias voltage and a region where thermal current over the barrier is dominant at large bias voltage. A dip in the dI/dV curve was observed in the tunneling region in the source-drain voltage (V(SD)) range from - 5 to 5 mV. In a different sample, periodic and reproducible staircaselike steps with a periodicity DELTAV(SD) of 35 mV were observed. This phenomenon is related to he Coulomb staircase, which occurs when the capacitance of a quantum dot is very small.

Electron transport was studied in AlGaAs/GaAs wires fabricated using focused Ga-ion-beam implantation. Single-wire samples 0.2-10-mu-m wide and 20-mu-m long were prepared with various ion doses ranging 2 X 10(11)-4 X 10(12) cm-2; multiple-wire samples 0.1-0.3-mu-m wide and 10-mu-m long were prepared with an ion dose of 2 X 10(11) cm-2. Electron mobility is reduced in the narrow wires because of the implantation-induced damage, and this mobility degradation is diminished by reducing the ion dose. These behaviors are consistently explained in terms of a diffusive scattering effect inside the channel and at the sidewall of the channel. Mobility in wires with the 2 X 10(11) cm-2 ions is predominantly determined by the sidewall specularity. A 0.2-mu-m-wide wire with this ion dose exhibits a mobility of 2 X 10(5) cm2/(V s) and a specularity above 0.8. These values exceed those previously reported for wires fabricated using ion implantation and probably arise from the annealing employed in the present work. Conductance steps are observed with a single 0.2-mu-m-wide wire, and enhanced transconductance steps occur in multiple-wire samples. These behaviors are related to mobility modulation that occurs when one-dimensional subbands cross the Fermi level.